Delta-sigma modulators are divided broadly into a discrete-time delta-sigma modulator and a continuous-time delta-sigma modulator according to a position of a switch for sampling an input signal.
In a case of the continuous-time delta-sigma modulator, a sampling switch is disposed after a loop filter and the loop filter processes a continuous-time signal of an input signal. Thereby, an output of the loop filter is input into a quantizer via the sampling switch and a digital output from this quantizer needs to be fed back continuously to the loop filter after having been converted into an analog signal. Therefore, when there exists a large jitter component in a timing signal for determining timing for the analog conversion of the signal to be fed back to the loop filter, the jitter noise is added to the input signal. That results in a problem that a noise level of the digital output is increased.
As a measure for solving this problem characteristic to the continuous-time delta-sigma modulator and improving tolerance to jitter, it is very effective to use a DAC (digital-analog converter) called an SC (switched-capacitor) feedback DA (or SCR feedback DA) as shown in FIG. 3A, for example (e.g., non-patent reference 1 and non-patent reference 2). Here, the operation principle thereof will be described with reference to FIGS. 2 to 4B.
FIG. 2 shows a continuous-time delta-sigma modulator having an SC feedback DA 103 for a measure to improve the tolerance to jitter. A loop filter 101 receives a continuous-time signal to be processed, supplies an output thereof to a quantizer 102 via a switch SW1 which samples the output in response to a clock CLK, and supplies a digital output from the quantizer 102 to the SC feedback DA 103 as a timing signal for the analog conversion. The SC feedback DA 103 generates a current to be fed back to the loop filter 101 from the digital signal output from the quantizer 102 and a first reference voltage Vref which determines a maximum level of a voltage signal to be fed back.
FIG. 3A is an example of a specific circuit of the feedback DA 103. When a switch SW2 is connected to an a-terminal, charge is once stored in a capacitor Cfb by the reference voltage Vref, and when the switch SW2 is switched to a b-terminal according to the output of the quantizer 102, the charge stored in the capacitor Cfb is fed back to the loop filter 101 via a resistor Rfb. The maximum current value at a moment when the switch SW2 is switched to the b-terminal is Vref/Rfb and then the current value is attenuated with a time constant τ=Rfb×Cfb (FIG. 3B).
On the other hand, FIG. 4A shows an example of a specific circuit of another type of the DAC called a SI (switched-current) feedback DA. The SI feedback DA is constituted by a fixed current source 401 and a switch SW3. When the switch SW3 is closed according to the output of the quantizer 102, the charge is fed back to the loop filter 101 by a current Ifb from the fixed current source 401.
Here, since the output of the quantizer 102 is generated in response to the sampling clock CLK, the output of the quantizer 102 has a temporal fluctuation when a jitter is superimposed to this clock CLK. Therefore, a length of a duration in which the charge is fed back to the loop filter 101 has also fluctuation. Thereby, a charge Qsc or Qsi, fed back to the loop filter 101 every CLK period Ts, changes slightly by an effect of this fluctuation. When an amount of this slight change is denoted by ΔQsc or ΔQsi, ratio of ΔQsc to Qsc in the feedback DA is outstandingly smaller than ratio of ΔQsi to Qsi, where the SC feedback DA feeds back most of the charge to be fed back to the loop filter 101 in the first half of the feed back duration, even compared in the same amount of the fluctuation, as apparent from FIG. 3B or FIG. 4B.
Therefore, the SC feedback DA has the much tolerance to jitter and a very effective circuit for the continuous-time delta-sigma modulator, compared with the SI feed back DA.
Note that a half of the CLK period Ts is represented as the duration for the charge feedback in FIGS. 3B and 4B, the duration is not limited to this value.
Non-patent reference 1: Maurits Ortmanns, “A Continuous-Time ΣΔ Modulator With Reduced Sensitivity to Clock Jitter Through SCR Feedback”, IEEE Trans. Circuits Syst. I, Regular Papers, vol. 52, No. 5, MAY 2005
Non-patent reference 2: Robert H. M. van Veldhoven, “A Triple-Mode Continuous-Time ΣΔ Modulator With Switched-Capacitor Feedback DAC for a GSM-EDGE/CDMA2000/UMTS Receiver”, IEEE Journal of Solid-State Circuits, vol. 38, No. 12, December 2003